A Low-Power High-Performance 64-Bit Booth Multiplier for Optimized Circuit Design

Author(s)	Ms. Govindu Kiranmayi, Dr. P. Ranjith Kumar
Country	India
Abstract	Using a Recurrent Binary Partial Products Generator approach, we may lower the maximum rank of the complete item cluster produced by a radix-16 Enhanced Booth without increasing the time of the fractional item manufacturing Block. Multipliers encoded on a single line. For n = 64-bit unregistered operands, we show an optimisation for simultaneous radix-16 (adjusted) Booth recoded multiplier, which brings the maximum height of the intermediary item sections down to [n/4]. Here, we see a departure from the standard upper limit of [(n + 1)/4]. The result is a one-unit reduction in the height of the tallest individual. Arithmetic multipliers improve the visibility of an ALU and processor. To test the efficacy of the proposed approach, we juxtapose it with the Normal Booth Multiplier. Rational amalgamation was effective in terms of space, time, and power. To construct the job, we will use Verilog. The Xilinx ISE instrumentation is used for the simulation and synthesis.
Keywords	The normal Booth multiplier, Modified Booth encoding multiplier, Booth recoded multiplier and alternatives.
Field	Engineering
Published In	Volume 17, Issue 3, July-September 2026
Published On	2026-07-20

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