Design of an Energy-Efficient Carry Select Adder for High-Performance Digital Systems

Author(s)	Mr. Pilli Charles Finny, Mr. T. Ravikanth
Country	India
Abstract	Modern mathematical and logical units aren't worth their salt unless they can do basic algorithmic operations like multiplication and addition quickly and accurately. Digital signal processing, AI, neural networks, and ML all rely on multiplication as their primary function. Filters have new potential as data storage components in the digital age. Full adders are the most popular choice for digital filter implementations. The digital filter is implemented using PPA in this project. The sklansky adder outperforms other PPAs in terms of efficiency. Kogge Stone Adder encounters more hardware complexity during implementation. Because of this, simplifying the sklansky adder's design is essential. A comparison was undertaken between several characteristics, including latency and the number of logic gates. The suggested design above uses a number of characteristics to simplify the hardware. A new logic structure and RCA construction for the BTA are proposed based on the analysis's conclusions. The comparison shows that the proposed RCA architecture is better than the current RCA in terms of space, latency, and energy efficiency.
Keywords	Binary tree adders, kogge stone adder, Carry Select Adder, Self Adaptive Reconfigurable Array and carry choose array adder.
Field	Engineering
Published In	Volume 17, Issue 3, July-September 2026
Published On	2026-07-20

About IJSAT Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics	Join as a Reviewer Editors & Reviewers Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us	Message on WhatsApp	+91-9687-182-185	editor@ijsat.org

International Journal on Science and Technology