Formal Signoff for Digital State Machines: Deadlock Detection and Coverage Convergence

Author(s)	Aparna Mohan
Country	United States
Abstract	Formal signoff for digital state machines (DSMs) is a critical step in verifying control-intensive hardware components for deadlock freedom and comprehensive state coverage. As systems become more concurrent and safety-critical, simulation alone is no longer sufficient. This review explores the theoretical underpinnings, tool workflows, experimental benchmarks, and current research in deadlock detection and coverage convergence using formal methods. Ten influential studies are summarized, and a proposed co-verification framework is presented. Experimental results reveal key trade-offs and bottlenecks in state exploration and convergence efficiency. The article concludes by outlining emerging directions such as machine learning-guided proof acceleration, compositional verification, and post-silicon formal monitors.
Keywords	Formal verification, FSM signoff, deadlock detection, coverage convergence, bounded model checking, symbolic execution, RTL verification, reinforcement learning, state exploration, post-silicon validation
Field	Engineering
Published In	Volume 16, Issue 1, January-March 2025
Published On	2025-02-08
DOI	https://doi.org/10.71097/IJSAT.v16.i1.7767
Short DOI	https://doi.org/g9zddc

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International Journal on Science and Technology