International Journal on Science and Technology

E-ISSN: 2229-7677   •   Impact Factor: 9.88

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Call for Paper Volume 16 Issue 4 October-December 2025 Submit your research before last 3 days of December to publish your research paper in the issue of October-December.
Submit Research Paper Join as a Reviewer

Plagiarism is checked by the leading plagiarism checker TurnItIn

Call for Paper

Volume 16 Issue 4
October-December 2025

Submit your research paper

Indexing Partners
Academia Advanced Sciences Index Bielefeld Academic Search Engine CiteSeer DRJI Google Scholar Independent Search Engine & Directory Network ISI (International Scientific Indexing) Issuu Mendeley Research Networks
RefSeek ResearcherId - Thomson Reuters ResearchGate Scirus Scribd Semantic Scholar UTeM - Universiti Teknikal Malaysia Melaka Wiki for Call for Papers WorldCat Zenodo

PyEdge-DNN: A Python Framework for Automated Generation and Deployment of FPGA-Accelerated DNNs for Edge Computing

Author(s) Ms. LANKA YAMINI SWATHI, Mr. K VENKATA RAO
Country India
Abstract The proliferation of Deep Neural Networks (DNNs) in Internet of Things (IoT) and Edge Computing applications necessitates low-power, high-performance hardware acceleration. . In this section, we will delve into the key concepts that define the role of FPGAs in edge computing. Field-Programmable Gate Arrays (FPGAs) have found a myriad of applications in edge computing due to their ability to accelerate specific workloads efficiently and with low latency. Field-Programmable Gate Arrays (FPGAs) are ideal candidates for this role due to their parallel processing capabilities and energy efficiency. However, the development of FPGA-based DNN accelerators remains a complex task, requiring expertise in hardware design and High-Level Synthesis (HLS) tools. This paper presents PyEdge-DNN, a Python-based framework that automates the generation, customization, and deployment of DNN topologies on FPGA platforms for edge applications. The framework, operating within a Jupyter Notebook environment on Xilinx PYNQ boards, allows users with minimal hardware knowledge to define a DNN model. It then automatically generates optimized Hardware Description Language (HDL) code through HLS, synthesizes the design, and deploys the resulting bitstream for acceleration. Experimental results demonstrate that a 784-32-32-10 multilayer perceptron network generated by our framework achieves a 59.8× speedup compared to a software implementation running on the embedded ARM CPU, while consuming less than 0.266W of power. This work significantly lowers the barrier to implementing efficient, custom DNN accelerators on edge devices.
Keywords Deep Neural Networks (DNN), FPGA, Edge Computing, IoT, High-Level Synthesis (HLS), PYNQ, Hardware Acceleration, Automation, Python
Field Engineering
Published In Volume 16, Issue 4, October-December 2025
Published On 2025-10-10
View / Download PDF File

Share this


CrossRef

CrossRef DOI is assigned to each research paper published in our journal.

IJSAT DOI prefix is
10.71097/IJSAT

Downloads
Research Paper Format Copyright Permission Form and Undertaking Form Cover Page Vol 16 Isu 3Cover Page Vol 16 Isu 2Cover Page Vol 16 Isu 1

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA Open Access

About IJSAT
Fees & Payment
Current Issue
Publication Archive 		Submit Research Paper
Track Submission Status
Publication Guidelines
Publication Ethics
Peer Review & Plagiarism 		Join as a Reviewer
Editors & Reviewers
Reviewer Referral Program
Get Reviewer Membership Certi. 		Website/Journal Policies
Usage Policy
Content Policies
Privacy Policy
Contact Us Message on WhatsApp +91-9687-182-185 editor@ijsat.org