Analysis and Implementation of Low Power Techniques in Viterbi Decoder Design

N V V K PRASAD; DARAM ANITHA KUMARI; THOTAKURA RENUKA

doi:10.71097/IJSAT.v16.i4.8911

Analysis and Implementation of Low Power Techniques in Viterbi Decoder Design

Author(s)	Mr. N V V K PRASAD, DARAM ANITHA KUMARI, THOTAKURA RENUKA
Country	India
Abstract	Rapid developments in the field of wireless communication have created a rising demand for Viterbi decoder with long battery life, low power dissipation and low weight. Despite the significant progress in the last decade, the problems of power dissipation in the Viterbi decoder still remains challenging and require further technical solutions. Hence this research focuses on designing low power VLSI (Very Large Scale Integration) architectures for the Viterbi decoder for a constraint length of K=3 and discuss their performances in terms of power, speed and area. The convolutional encoders are designed for constraint length of K=3 to7. Thus the performance of the Viterbi decoder is improved by low power VLSI techniques. In order to reduce the power consumption and to increase the speed of the Viterbi decoder repeated iterations are performed at the same clock transition by unfolding algorithm. This unfolding algorithm is applied at the bit level to generate digit-serial architecture, which processes multiple words per clock cycle. The obtained results are compared with the existing 2 bit level pipe lined look ahead technique. It is observed that the proposed method reduced power consumption by 25.76% with 10.09% increase in speed. The limitation of this method is addressed by wave pipe lining technique and it is implemented to increase the speed of the architecture as the idle time of the non critical paths is reduced.The combined technique of Self Reset Logic (SRL) with wave pipe lining is used to design the architecture for the Viterbi decoder to reduce the power dissipation. Power consumption of the wave pipelining work is reduced by a factor of 72.31% when compared to the existing single rail domino logic. The area of the decoder increases with respect to its advantage of increase in speed.VLSI architecture for a Viterbi decoder based on GDI (Gate Diffusion Input) is designed to minimize the number of transistors and transitions. Thus the problem of high gate density in SRL based design is addressed by the GDI approach. GDI method yielded better results when compared to the average power consumption of Viterbi decoder with that of CMOS logic. Power consumption is reduced by 29%, for a frequency of 25 MHz and the area is reduced by 66%.Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). The performance of the asynchronous Viterbi decoder showed 56.20% less power consumption and has a frequency of 425 MHz when compared to that of synchronous design
Keywords	LOW POWER,DECODER
Field	Engineering
Published In	Volume 16, Issue 4, October-December 2025
Published On	2025-10-24
DOI	https://doi.org/10.71097/IJSAT.v16.i4.8911
Short DOI	https://doi.org/g98ndc

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Analysis and Implementation of Low Power Techniques in Viterbi Decoder Design

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